1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2011-102400, filed Apr. 28, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, a size of a semiconductor device such as a dynamic random access memory (DRAM) has decreased. Thereby, when a transistor is configured to have a short gate length, a short channel effect of the transistor becomes remarkable, a sub-threshold current increases, and a threshold voltage (Vt) of the transistor decreases.
When an impurity concentration of a semiconductor substrate is increased to suppress the threshold voltage (Vt) of the transistor from decreasing, a junction leak current may increase.
For this reason, when the DRAM is used as the semiconductor device and a size of a memory cell of the DRAM is decreased, a refresh characteristic is severely deteriorated.
As a structure to resolve the above problems, a so-called trench gate type transistor (referred to as a “recess channel transistor”) in which a gate electrode is buried in a groove formed on the side of a main surface of a semiconductor substrate is disclosed in Japanese Laid-Open Patent Publications Nos. 2006-339476 and 2007-081095. By configuring the transistor as the trench gate type transistor, an effective channel length (gate length) can be physically and sufficiently secured and a DRAM that has a fine cell in which a minimum processing dimension is 60 nm or less can be realized.
Japanese Laid-Open Patent Publication No. 2007-081095 discloses a DRAM that includes two grooves formed in a semiconductor substrate to be adjacent to each other, gate electrodes formed in the grooves through a gate insulating film, a first impurity diffusion region formed in a main surface of the semiconductor substrate positioned between the two gate electrodes as an impurity diffusion region common to the two gate electrodes, and a second impurity diffusion region formed in the main surface of the semiconductor substrate positioned at an element isolation region side of the two gate electrodes.
In the DRAM that has the trench gate type transistor described in Japanese Laid-Open Patent Publications Nos. 2006-339476 and 2007-081095, a channel region of the transistor is formed on three surfaces of both sides and a bottom surface of a trench.
The inventors have found that an on-state current of the transistor cannot be sufficiently secured and a normal operation of the DRAM becomes difficult when the size of the transistor having the above-described configuration is further decreased. This phenomenon is generated because the channel region of the transistor is formed on the three surfaces forming the trench and channel resistance increases, as described above.
If an arrangement pitch of the trench gate is narrowed, when a certain transistor is operated, an operation state of the transistor interferes with another transistor adjacent to the transistor and the transistor cannot be operated independently.
This phenomenon is generated because the channel region is formed between the adjacent trench gates.
In the trench gate type transistor, because the gate electrode is formed to protrude to an upper side of a surface of the semiconductor substrate, it becomes very difficult to form a bit line or a capacitor to be formed in the following process due to the protruding gate electrode and it becomes difficult to manufacture the DRAM.
Accordingly, there is a demand to provide a semiconductor device and a manufacturing method thereof that can sufficiently secure an on-state current of a transistor, prevent operation interference of adjacent transistors, and resolve manufacturing difficulty in the DRAM including the transistor using the trench.